DDR DQS to CLK delay 관련

vivado 2017.4 zynq-zybo-z7 board 로 진행중 아래와 같은 error를 만났다.

[PSU-1] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.05 . PS DDR interfaces might fail when entering negative DQS skew values.

[PSU-2] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.05 . PS DDR interfaces might fail when entering negative DQS skew values.

[PSU-3] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 has negative value -0.05 . PS DDR interfaces might fail when entering negative DQS skew values.

[PSU-4] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 has negative value -0.05 . PS DDR interfaces might fail when entering negative DQS skew values.

 

일단 검색결과 보면 2개까지만 에러가 나오는게 있었다 

2ea 있는거는 zed board, ddr2, 512MB짜리인데 내부 구조상 DQ 그룹이 2개 뿐인듯 하다. JEDEC 표준 참고해서 확인하면 될거같다. 

4ea 있는건 사용중인 DDR3의 stack? DQ 그룹이 4ea 있는걸거고

byte lane 단위를 구성하는 요소 중 실제 data를 나타내는 DQ(0~7)가 8ea(8bit)를 가지고 있기때문에 1  DQ이유는 2개 에러나오는 보드는  512MB DDR이고 ?내꺼는  2배인 1024MB DDR 이라 4ea?

 

negative DQS 도 DDR에서는 지원하니깐 문제가 없다고 하는 답변

비슷한 문제를 격는사람들중에 빡쳐서 이런글을 쓰니깐

답변을 해줬다. 

@thobie, the bare-metal purchase option for the Zybo was done to enable a lower price point for those who do not require the accessories. For the rest of our customers, adding the Accessory Kit is recommended during the purchase process.

You are not the first and the last to complain about version compatibility. It is economically unfeasible for us to update all support projects, IP and support packages provided for free four times per year for each Vivado version. Instead we made a commitment to consider the last Vivado release in each year stable and do a once-a-year update cycle. In that regard, 2017.4 is the version we are upgrading projects to. There is a question whether OOB designs should be updated at all, or kept at the version which generated the binary image shipped with the board.

The board presets are not versioned for Vivado (no version-specific releases in our git repo), because these should be forward-compatible with Vivado versions. The critical warning itself related to CK-to-DQS delays being negative appears starting with 2017.4. The negative values are due to CK trace being shorter than any of the four DQS traces.

In the early days of Zynq board design negative values where listed as sub-optimal, but not erroneous. Tree topology instead of fly-by was also among the routing recommendations for DDR3 layouts. So the Zybo was designed with this sub-optimal layout due to space constraints. During Write Leveling calibration, 0 is used as an initial value instead of the negative preset delays. After calibration, if the skew is still too low, the clock is inverted. See ug585 pg 316 for more details. All Zybos shipped to customers are functionally tested and pass the DDR3 calibration process.

Xilinx recommendations changed in the mean time, both in terms of routing topology and delay values. A trace of this can be found here: https://www.xilinx.com/support/answers/53039.html. The > 0ns requirement was introduced to be in line with non-Zynq MIG-based designs, where negative delays were never permitted.

Since these delays are board-dependent, we would need to re-design the board to make the delay positive. This is impossible with the current form-factor.

Another option would be modifying the board preset file and forcing a zero value instead of the actual delay. The tools seem to be using zero anyway for calibration. This will have to be thoroughly verified first.

 

보드제작당시에는 negative 값이 나와도 되었고 layout 공간이 없어 fly-by topology대신 T분기 topology를 사용하여 제작을 했고 

그래서 CLK 라인이 DQS보다 짧게 되어 negative 값이 나오는 상황이였으나 2017.4버전부터 rule이 음수가 나오면 안되게 바뀌어 나타나는 오류라고 한다.  어차피 negative로 되어있으면 시스템에서 0부터 write leveling 하게 되는거니 0으로 변경해서 사용하면된다고 한다. 실제로 그렇게 하니깐 된다. 

 

*DDR3 routing guide

https://logic-fruit.com/wp-content/uploads/2018/06/DDR-routing-Topology-1.pdf

*ug585문서 316페이지에 자세한 설명이 있다. 

 

https://www.xilinx.com/support/answers/53039.html

AR# 53039: 14.3 EDK, Zynq-7000 DDRC - Why is the PS7 DDR Configuration limit DQS to Clock delay to -.100ns/0ns?

 

https://www.xilinx.com/support/answers/46778.html

AR# 46778: Zynq-7000 - How do I configure the PS DDRC board parameters?

 

 

아래는 참고

---