목록하드웨어 (2)
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DDR DQS to CLK delay 관련
vivado 2017.4 zynq-zybo-z7 board 로 진행중 아래와 같은 error를 만났다. [PSU-1] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.05 . PS DDR interfaces might fail when entering negative DQS skew values. [PSU-2] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.05 . PS DDR interfaces might fail when entering negative DQS skew values. [PSU-3] Parameter : PCW_UIPARAM_DDR_DQ..
Daisy chain, multi drop, fly-by Topology
DDR3 설정을 보면 DQS to CLK delay가 있다. fly by Topology 때문에 생기는 delay 값으로 생각하면 될거같고 설명하는 여러 topology가 있어 찾아봤다. 더보기 Fly-by Topology DDR3/4 fly-by topology is similar to daisy chain or multi-drop topology, but it includes very short stubs to each memory device in the chain to reduce the reflections. The advantage of fly-by topology is that it supports higher-frequency operation and improves signal integ..